This invention is in the field of flash memory devices, and is more specifically directed to data communications between flash memory devices and memory controllers in electronic systems.
As well known in the art, “flash” memories are electrically-erasable semiconductor memory devices that can be erased and rewritten in relatively small blocks, rather than on a chip-wide or large-block basis as in previous electrically-erasable programmable read-only memory (EEPROM) devices. As such, flash memory has become especially popular for applications in which non-volatility (i.e., data retention after removal of power) of the stored data is essential, but in which the frequency of rewriting is relatively low. Examples of popular applications of flash memory include portable audio players, “SIM” card storage of telephone numbers and phone activity in cellular telephone handsets, “thumbkey” removable storage devices for computers and workstations, storage devices for digital cameras, and the like.
An important recent advance in semiconductor non-volatile memory technology is the arrangement of the flash memory cells as “NAND” memory rather than as “NOR” memory. As known in the art, NOR flash memory refers to the conventional arrangement of a column of memory cells in parallel between a bit line and a source line. Access of a specific cell in a NOR column is made by driving its word line (control gate) active while holding the other cells in the column off, so that the current between the bit line and source line is determined by the state of the accessed cell. Memory cells in a column of NAND memory, on the other hand, are connected in series between the bit line and the source line. Accessing of a specific cell in a NAND column thus requires turning on all of the cells in the column with active word line levels, and applying an intermediate word line level to the cell to be accessed, such that the current between the bit line and source line is, again, determined by the state of the accessed cell. As well known in the art, the chip area required per bit of NAND flash memory is much reduced from the area per bit of NOR flash memory, primarily because fewer conductors (and therefore contacts) are required for a column of NAND memory relative to NOR memory; in addition, access transistors can be shared among a large number of cells in the NAND arrangement. Additionally, conventional NAND flash memory is conveniently accessed serially, for example by sequentially accessing cells along the columns, rather than as a random access memory as in the case of NOR memory. NAND memory is thus especially well-suited for music and video storage applications
Another important recent advance in the field of flash memory is referred to in the art as the multilevel program cell (MLC). According to this approach, more than two data states are made possible for each memory cell, simply by more finely controlling the programming of the cell. In conventional binary data storage, each memory cell is programmed into either a “0” or a “1” state. Reading of such binary cells is accomplished by applying a single control voltage to the control gate of the addressed memory cell so that the transistor conducts if programmed to a “1” state, but remains off in the “0” state; sensing of the conduction through the addressed memory cell thus returns the programmed state of the cell. In contrast, according to a typical example of the MLC approach, four possible states are defined for each memory cell, typically corresponding to binary values 00, 01, 10, 11. In effect, the two intermediate states correspond to two levels of partial programming of the cell between the fully erased and fully programmed states. Some implementations of MLC flash memory with up to eight possible states, or three binary bits, per cell are known. The ability to store two or three bits of data on each memory cell immediately doubles or triples the data capacity of a flash memory chip. Examples of MLC flash memory cells and memories including such MLC cells are described in U.S. Pat. No. 5,172,338, and U.S. Pat. No. 6,747,892 B2, both commonly assigned herewith and incorporated herein by this reference.
The combination of MLC technology with the efficiencies of NAND flash memory architectures has resulted in significantly reduced cost per bit for semiconductor non-volatile storage, as well as improved system reliability, and a higher data capacity and system functionality for a given form factor. However, despite these important improvements, the data transfer rates to and from conventional flash memory devices have not kept pace. Certain modern applications of flash memory are especially sensitive to data transfer rates, especially as the data capacity increases. For example, the resolution of high-performance, professional level, digital still cameras now can exceed 10 megapixels, for which the advances of MLC NAND flash memory technology are welcome. However, the “shutter lag” between successive image captures depends on the data transfer rate of the image data from the sensor into flash memory. This delay time between images (which, to the camera user, is considered as an independent parameter, not dependent on image resolution) is becoming a critical factor in these cameras. Especially as the image resolution continues to increase, it has been observed that conventional data transfer times are not adequate to achieve the desired delay time between images. Nor are the data transfer times into and out of conventional flash memory competitive with those of modern magnetic disk drives, which is of course another desirable new application for flash memory. Accordingly, in order for flash memory to meet the needs of modern high-performance digital still cameras, or to serve as solid-state mass storage in modern high-performance electronic systems, it will become necessary to achieve much higher data transfer rates to and from flash memory devices.
An example of a conventional data transfer approach for flash memories is described in the datasheet 2 GBIT (256M×8 BITS) CMOS NAND E2PROM, part number TH58NVG1S3AFT05 (Toshiba, 2003). This conventional approach involves an eight-bit data bus, with one bit presented on each data output per cycle of a read enable clock, synchronous with the falling edge of that read enable clock. Also as described in that datasheet, this conventional approach involves a 3.3 volt logic standard, such that the minimum high logic level output voltage (VOH) is 2.4 volts and the maximum low logic level output voltage (VOL) is 0.4 volts. This device provides a maximum data rate of 20 MHz. It is believed that this data rate is not an adequate data rate for mass storage in personal computer systems, and as such these conventional flash memories would not be suitable for disk drive replacement.
By way of background, some conventional dynamic random access memories (RAMs) implement so-called “double data rate”, or “DDR”, data transfer techniques. As known in that art, DDR data transfer involves the transfer of one or more data bits (depending on the number of bus lines) synchronously with both the rising and falling edges of the corresponding data strobe, or clock. DDR data transfer thus communicates data at twice the data rate of conventional synchronous data transfer, which is synchronous with only one of the clock edges (rising or falling edge). In addition, conventional DDR dynamic RAMs utilize source-synchronous data strobes, in which the RAM device itself generates the data strobe for reads from the memory (while the external circuitry generates the data strobe for writes to the memory). However, this doubling of the input/output switching rate increases the power consumption of data transfer, approaching twice that of single-data rate communications.
Power consumption in modern electronic systems is a substantial concern, however, and the driving of buses and conductors in transferring data among integrated circuit devices in a system is a significant contributor to overall system power consumption. As is fundamental in the art, the power consumption of output driver circuits, for driving external conductors, relates directly to the switching rate of digital signals to be driven. Increasing the data transfer rate to approach those of modern magnetic disk drives, as mentioned above, thus will require a corresponding increase in the power consumed by such data transfer, keeping all other parameters equal. This increased power consumption requires larger driver and receiver devices, improved heat dissipation in system applications, and the like, all of which add cost to the overall system. Even if these changes are made, the increased power consumption from high-speed data transfer is undesirable for portable electronic systems, such as digital cameras, laptop computers and workstations, wireless telephone handsets, personal digital audio players, and similar battery-powered devices.
By way of further background, a communications protocol known as Ultra DMA Mode is known in the art, for communications to and from a flash memory card, such as a COMPACT FLASH, or CF+, flash memory card. FIG. 1 illustrates such a conventional flash memory card, constructed and operating according to the well-known standard CF+ and CompactFlash Specification Revision 3.0 (CompactFlash Association, 2004). As shown in FIG. 1, flash memory card 2, which in this example is constructed as a COMPACT FLASH storage card according to this standard, contains one or more flash memory modules 2, and single chip memory controller 4. Flash memory module 4 communicates data to and from memory controller 6 over bus data_I/O, and receives and issues control signals to and from memory controller 6 over control bus ctrl. In this example, the data transfer approach described in the above-referenced Toshiba datasheet corresponds to these communications over the data_I/O and ctrl buses between flash memory module 4 and memory controller 6. Memory controller 6 communicates with a host device (e.g., digital camera, digital audio player, personal computer, etc.) over host interface HOST_IF. The above-referenced CF+ and CompactFlash Specification describes communications over host interface HOST_IF, including according to the Ultra DMA Mode (“UDMA”). As described in that specification, UDMA communications are carried out in a special operating mode, initiated by the driving of a signal on a control line (UDMARQ) by the agent (host or memory card 2) that desires such communication. Also as described in that specification, UDMA data transfers are source-synchronous, in that the agent (memory card 2 or host system) that is placing the data onto bus HOST_IF is also issuing the data strobe signal. In addition, also as described in that specification, both rising and falling edges of the strobe signal are used in the transfer of data under the UDMA mode of operation.
However, it has been observed, in connection with this invention, that even with the UDMA mode for the host interface in the flash card of FIG. 1, the data transfer rate between the memory module 4 and memory controller 6 will limit the overall performance of memory card 2. However, the speeding up of data transfer at that interface according to conventional techniques will also greatly increase power consumption within memory card 2. In addition, it is known in the art that modification to input/output interfaces of memory integrated circuits will greatly limit the usability of such integrated circuits, adding cost from the standpoint of inventory control and design overhead.
By way of further background, other approaches toward improving the data transfer rate between a memory module and a memory controller, in the context of flash memory modules, are described in copending and commonly assigned applications Ser. No. 11/379,895 filed Apr. 24, 2006, entitled “Method of High-Performance Flash Memory Data Transfer”; Ser. No. 11/379,910, filed Apr. 24, 2006, entitled “High-Performance Flash Memory Data Transfer”; Ser. No. 11/424,573 filed Jun. 16, 2006, entitled “Method of High-Performance Flash Memory Data Transfer”; and Ser. No. 11/379,581 filed Jun. 16, 2006, entitled “High-Performance Flash Memory Data Transfer”.